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motorola semiconductor technical data pc33886 simplified application diagram this document contains informat ion on a product under development. motorola reserves the right to change or discontinue this product without notice. ? motorola, inc. 2002 order this document from analog marketing rev 0, 06/2002 preliminary information 5.2 a h-bridge the 33886 is a monolithic h-bridge ideal for fractional horsepower dc- motor and bi-directional thrust solenoid control. the ic incorporates internal control logic, charge pump, gate drive, and low r ds(on) mosfet output circuitry. the 33886 is able to control continuous inductive dc load currents to 5.2 a. output loads can be pulse width modulation (pwm) controlled at frequencies to 10 khz. a fault status output reports undervoltage, overcurrent, and overtemperature conditions. two independent inputs control the two half- bridge totem-pole outputs. two disable inputs force the outputs to tristate (exhibit high impedance). the 33886 is parametrically specified over a temperature range of -40 c t a 125 c, 5.0 v v pwr 28 v, and is available in an economical surface mount package. features ? direct replacement for mc33186dh1 in the hsop20 package ? 5.0 v to 36 v operation ? 120 m ? r ds(on) h-bridge switches ? ttl/cmos compatible inputs ? pwm frequencies to 10 khz ? automatic pwm overcurrent limiting ? output short circuit protection ? overtemperature output current reduction with shutdown ? undervoltage shutdown ? fault status reporting 5.2 a h-bridge ordering information device temperature range (t a ) package pc33886dh/r2 -40 to 125c 20 hsop dh suffix 20-lead hsop case 979c pc33886 pin connections 1agnd 2fs 3in1 4v pwr 5v pwr 6out1 7out1 8 dnc 9pgnd 10 pgnd 11 pgnd 12 pgnd 13 d2 14 out2 15 out2 16 v pwr 17 c cp 18 d1 19 in2 20 dnc motor c cp v pwr v pwr in1 in2 d1 d2 fs out1 out2 gnd mcu or dsp 5.0 v
pc33886 motorola analog integrated circuit device data 2 figure 1. pc33886 internal block diagram pin function description hsop pin name description 1 agnd low current analog signal ground. 2 fs open drain active low fault status output requiring a pull-up resistor to 5.0 v. 3 in1 true logic input control of out1 (i.e., in1 logic high = out1 high). 4, 5, 16 v pwr positive power source connection. 6, 7 out1 h-bridge output 1. 8, 20 dnc connect these pins to ground in the application. t hey are test mode pins used in manufacturing only. 9C12 pgnd device high current power ground. 13 d2 active low input used to simultaneously tristate disable both h-bridge outputs. when d2 is logic low, both outputs are tristate. 14, 15 out2 h-bridge output 2. 17 c cp external reservoir capacitor connection for internal charge pump. 18 d1 active high input used to simultaneously tristate dis able both h-bridge outputs. when d1 is logic high, both outputs are tristate. 19 in2 true logic input control of out2 (i.e., in2 logic high = out2 high). charge pump over- temperature 5.0 v regulator gate drive cur rent li mit, overcurrent sense ci rc uit undervoltage out1 out2 in1 in2 d1 d2 fs c cp v pw r pgnd agnd control logic 80 ua (each) 25 ua
motorola analog integrated circuit device data pc33886 3 maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit power supply voltage normal operation (steady-state) transient (note 1) v pwr(ss) v pwr(t) 36 40 v input voltage (note 2) v in 7.0 v fs status output (note 3) v fs 7.0 v continuous output current (note 4) i out(cont) 5.2 a esd voltage human body model (note 5) machine model (note 6) v esd1 v esd2 2000 200 v storage temperature t stg -65 to 150 c ambient temperature (note 7) t a -40 to 125 c operating junction temperature t j -40 to 150 c lead soldering temperature (note 8) t solder 260 c approximate junction-to-board thermal resistance (note 9) r j-b ~5.0 c/w notes: 1. device will survive the transient overvoltage indicated for a maximum duration of 500 ms. 2. exceeding the input voltage on in1, in2, d1, or d2 may cause a malfunction or permanent damage to the device. 3. exceeding the pull-up resistor voltage on the open drain fs pin may cause permanent damage to the device. 4. continuous output current capability so long as juncti on temperature is 150 c. 5. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 6. esd2 testing is performed in accordance with the machine model (c zap = 100 pf, r zap = 0 ? ). 7. the limiting factor is junction temperature, taking into a ccount the power dissipation, thermal resistance, and heat sinking. 8. lead soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersion soldering. exceeding these li mits may cause malfunction or permanent damage to the device. 9. exposed heat sink pad plus the power and ground terminals comprise the main heat conduction paths. the actual r j-b (junction-to-pc board) values will vary depending on solder thickness and composit ion and copper trace.
pc33886 motorola analog integrated circuit device data 4 static electrical characteristics characteristics noted under conditions 5.0 v v pwr 28 v and -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power supply operating voltage range steady-state (note 10) transient (t < 500 ms) (note 11) v pwr(ss) v pwr(t) 5.0 C C C 36 40 v v standby supply current v en = 5.0 v, i load = 0 a i pwr(standby) CC20ma threshold supply voltage switch-off switch-on hysteresis v pwr(thres-off) v pwr(thres-on) v pwr(hys) 4.15 4.5 150 4.4 4.75 C 4.65 5.0 C v v mv charge pump charge pump voltage v pwr = 4.15 v v pwr < 40 v v cp -v pwr 3.35 C C C C 20 v v control inputs input voltage (in1, in2, d1, d2 ) threshold high threshold low hysteresis v ih v il v hys 3.5 C 0.7 C C 1.0 C 1.4 C v v v input current (in1, in2, d1) (note 12) v in = 0 v i in -200 -80 C a d2 input current (note 13) v d2 = 5.0 v i d2 C 25 100 a notes: 10. parameter is guaranteed by design but not production tested. 11. device will survive the transient overvoltage indicated for a maximum duration of 500 ms. 12. inputs in1, in2 and d1 have independent internal pull-up current sources. 13. the d2 input incorporates an active internal pull-down current sink.
motorola analog integrated circuit device data pc33886 5 static electrical characteristics characteristics noted under conditions 5.0 v v pwr 28 v and -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power outputs (out1, out2) output-on resistance (note 14) 5.0 v < v pwr < 28 v, t j = 25 c 8.0 v < v pwr < 28 v, t j = 150 c 5.0 v < v pwr < 8.0 v, t j = 150 c r out C C C 120 C C C 225 300 m ? m ? m ? output latch-off current (note 15) i latch-off 5.2 6.5 7.8 a output latch-off time t a 15 20.5 26 s output blanking time t b 12 16.5 21 s high-side overcurrent detection i ocd(h) 11 C C a low-side overcurrent detection i ocd(l) 8.0 C C a leakage current (note 16) v out = v pwr v out = gnd i out(leak) C C 100 30 200 60 a a free-wheeling diode forward voltage drop (note 17) i out = 3.0 a v f CC2.0v free-wheeling diode reverse recovery time (note 17) t rr 100 C C ns switch-off thermal shutdown hysteresis t lim t hys 175 C C 15 C C c c fault status (note 18) fault status leakage current (note 19) v fs = 5.0 v i fs (leak) CC10 a fault status set voltage (note 20) i fs = 300 a v fs (low) CC1.0v notes: 14. output-on resistance as measured from output to v pwr and gnd. 15. future product will exhibit the values indicated in this table. interim product exhibits a minimum of 6.0 a and a maximum of 8.5 a. 16. outputs switched off with d1 or d2 . 17. parameter is guaranteed by design but not production tested. 18. fault status output is an open drain output requiring a pull-up resistor to 5.0 v. 19. fault status leakage current is measured with fault status high and not set. 20. fault status set voltage is measured with fault status low and set with i fs = 300 a .
pc33886 motorola analog integrated circuit device data 6 dynamic electrical characteristics characteristics noted under conditions 5.0 v v pwr 28 v and -40 c t a 125 c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit timing characteristics pwm frequency (note 21) f pwm C C 10 khz maximum switching frequency during current limit (note 22) f max C C 20 khz output on delay (note 23) v pwr = 14 v t d(on) CC18s output off delay (note 23) v pwr = 14 v t d(off) CC18s output rise and fall time (note 24) v pwr = 14 v, i out = 3.0 a t f , t r 2.0 5.0 8.0 s disable delay time (note 25) t d(disable) CC8.0s over-current/temperature turn- off time (note 26) t fault C4.0Cs power- off delay time t pod C1.05.0ms notes: 21. the outputs can be pwm controlled from an external source. the pwm frequency is t he externally induced output switching freq uency, the maximum of which is limited by the internal charge pump. 22. the maximum switching frequency during current limit is internal ly implemented. the internal c ontrol produces a constant off -time pwm of the output. the output load current effects the maximum switching frequency. 23. output delay is the time duration from the midpoint of the in1 or in2 input signal to the 10% or 90% point (dependent on the transition direction) of the out1 or out2 signal. if the output is transiti oning high-to-low, the delay is from the midpoint of the input signal to the 90% point of the output response signal. if the output is transitioning low-to-high, the delay is from the midpoint of the inpu t signal to the 10% point of the output response signal. see figure 3. 24. rise time is from the 10% to the 90% level and fall time is from the 90% to the 10% level of the output signal. see figure 4 . 25. disable delay time is the time duration from the midpoint of the d (disable) input signal to 10% of the output tristate resp onse. see figure 3. 26. increasing output currents will become limited at 6.5 a. hard shorts will breach the 6.5 a limit, forcing the output into an immediate tristate latch-off. see figure 5 and figure 6. output current limiting will cause junction temperatures to rise. a junction temperature above 160 c will cause the output current limit to progressively "fold-back" (or decrease) to 2.5 a typical at 175 c where thermal latch-off will occur. see figure 7.
motorola analog integrated circuit device data pc33886 7 figure 2. output delay time figure 3. disable delay time figure 4. output switching time time 0 5.0 0 v pwr t d(on) 50% 90% 50% 10% v i n 1 , i n 2 ( v ) t d(off) v o u t 1 , 2 ( v ) t r 0 v pwr 90% 10% v o u t 1 , 2 ( v ) 10% 90% t f
pc33886 motorola analog integrated circuit device data 8 figure 5. output load current limiting versus time figure 6. pwm current limiting detail d 1 , l o g i c i n [0] [1] hard output short latch-off overcurrent (minimum) pwm current limiting (see figure 6.) 8.0 6.5 i l o a d , o u t p u t c u r r e n t ( a ) f s , f a u l t s t a t u s outputs tristate latched (h-bridge swi tc hes off) ti me d 2 , l o g i c i n [0] [0] [1] [1] i n , l o g i c i n [0] [1] in1 in2 in2 in1 outputs operational (per input control condit ion) 0 or overcurrent minimum threshold t a t b 8.0 time i l o a d , o u t p u t c u r r e n t ( a ) typical pwm load current limiting waveform hard output short latch-off t a = tristate output off time t b = current limit blank time 6.5
motorola analog integrated circuit device data pc33886 9 figure 7. maximum output current limiting versus temperature i m a x , o u t p u t c u r r e n t ( a ) 6.6 2.5 160 175 thermal shutdown t j , junction temperature ( o c)
pc33886 motorola analog integrated circuit device data 10 table 1. truth table the tristate conditions and the fault status are reset using d1 or d2 . the truth table uses the following notations: l = low, h = high, x = high or low, and z = high impedance (all output power transistors are switched off). device state input conditions status outputs d1 d2 in1 in2 fs out1 out2 forward l h h l h h l reverse l h l h h l h free wheeling low l h l l h l l free wheeling high l h h h h h h disable 1 (d1) h x x x l z z disable 2 (d2 )xlxxlzz in1 disconnected l h z x h h x in2 disconnected l h x z h x h d1 disconnected z x x x l z z d2 disconnected x z x x l z z undervoltage (note 27) x x x x l z z overtemperature (note 28) x x x x l z z overcurrent (note 28) x x x x l z z notes: 27. in the case of an undervoltage condition, the outputs tristate and the fault status is set logic low. upon undervoltage reco very, fault status is reset automatically or automatic ally cleared and the outputs are restored to their original operating condition. 28. when an overcurrent or overtemperature condition is detected, the power outputs ar e tristate latched-off independent of the input signals and the fault status flag is set logic low.
motorola analog integrated circuit device data pc33886 11 system/application information introduction numerous protection and operational features (speed, torque, direction, dynamic breaking, and pwm control), in addition to the 5.2 a output current capability, make the 33886 a very attractive cost-effective solution for controlling a broad range of fractional horsepower dc-motors. a pair of 33886 devices can be used to control bipolar stepper motors in both directions. in addition, the 33886 can be used to control permanent magnet solenoids in a push-pull variable force fashion using pwm control. the 33886 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding ac currents. as shown in figure 1, internal block diagram, the 33886 is a fully protected monolithic h-bridge with fault status reporting. for a dc-motor to run the input conditions need be as follows: d1 input logic low, d2 input logic high, fs flag cleared (logic high), with one in logic low and the other in logic high to define output polarity. the 33886 can execute dynamic breaking by simultaneously turning-on either the two high- side or the two low-side h-bridge switches; e.g., in1 and in2 logic high or in1 and in2 logic low. the 33886 outputs are capable of providing a continuous dc load current of 5.2 a from a 36 v v pwr source. an internal charge pump supports pwm frequencies to 10 khz. an external pull-up resistor is required for the open drain fs pin for fault status reporting. two independent inputs (in1 and in2) provide control of the two totem-pole half-bridge outputs. two disable inputs (d1 and d2 ) are for forcing the h-bridge outputs to a high impedance state (all h-bridge switches off). the 33886 has undervoltage shutdown with automatic recovery, output current limiting, output short-circuit latch- off, and overtemperature latch-off. an undervoltage shutdown, output short-circuit latch-off, or overtemperature latch-off fault condition will cause the outputs to turn-off (tristate) and the fault output flag to be set low. either of the d inputs or v pwr must be toggled to clear the fault flag. the overcurrent/overtemperature shutdown scheme is unique and best described as using a junction temperature dependent output current fold back protection scheme. when an overcurrent condition is experienced, the current limited output is ramped down as the junction temperature increases above 160 c, until at 175 c the output current has decreased to about 2.5 a. above 175 c, overtemperature shutdown (latch-off) occurs. this feature allows the device to remain in operation for a longer time with unexpected loads, but with regressive output performance at junction temperatures above 160 c. functional pin description pgnd and agnd power and analog ground pins. the power and analog ground pins should be connected together with a very low impedance connection. v pwr v pwr pins are the power supply inputs to the device. all v pwr pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. v pwr pins have an undervoltage threshold. if the supply voltage drops below a v pwr undervoltage threshold, the output power stage switches to a tristate condition and the fault status flag is set and the fault status pin voltage switched to a logic low. when the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins and the fault status flag is automatically reset logic high. fault status (fs ) this pin is the device fault status output. this output is an active low open drain structure requiring a pull-up resistor to 5.0 v. refer to table 1, truth table. in1, in2, d1, d2 these pins are input control pins used to control the outputs. these pins are 5.0 v cmos-compatible inputs with hysteresis. the in1 and in2 independently control out1 and out2, respectively. d1 and d2 are complimentary inputs used to tristate disable the h-bridge outputs. when either d1 or d2 is set (d1 = logic high or d2 = logic low) in the disable state, outputs out1 and out2 are both tristate disabled; however, the rest of the device circuitry is fully operational and the supply i pwr(standby) current is reduced to a few milli-amperes. see table 1, truth table , and static electrical characteristics table. out1, out2 these pins are the outputs of the h-bridge with integrated free-wheeling diodes. the bridge output is controlled using the in1, in2, d1, and d2 inputs. the outputs have pulse width modulated (pwm) current limiting above 6.5 a. the outputs also have thermal shutdown (tristate latch-off) with hysteresis as well as short circuit latch-off protection. a disable timer (time t b ) incorporated to detect currents that are higher than current limit is activated at each output activation to facilitate detecting hard output short conditions. see figure 6 .
pc33886 motorola analog integrated circuit device data 12 c cp charge pump output pin. a filter capacitor (up to 33 nf) can be connected from the c cp pin and pgnd. the device can operate without the external capacitor, although the c cp capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and pwm frequency. performance features short circuit or overcurrent protection if an output overcurrent condition is detected, the power outputs tristate latched-off independent of the input signal states and the fault status output flag is set logic low. if the d1 voltage changes from logic high to logic low or from logic low to logic high on d2 , the output switches on again and the fault status flag is reset (cleared) to a logic high state. the output stage will always switch into the mode defined by the input pins (in1, in2, d1, and d2 ), provided the device junction temperature is within the specified operating temperature. pwm current limiting the maximum current flow under normal operating conditions is limited to i max (5.2 to 7.8 a). when the maximum current value is reached, the output stages are tristated for a fixed time (t a ) of 20 s typical. depending on the time constant associated with the load characteristics, the output current decreases during the tristate duration until the next output on cycle occurs. see figure 6. the pwm current limitation value is dependent upon the device junction temperature. when -40 c < t j < 160 c, i max is between 5.2 and 7.8 a. when t j exceeds 160 c, the i max current decreases linearly down to 2.5 a typical at 175 c typical (or where the device reaches t lim ) and overtemperature shutdown occurs. see figure 7. this feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160 c. overtemperature shutdown and hysteresis if an overtemperature condition occurs, the power outputs are tristate latched-off independent of the input signals and the fault status flag is set logic low. if the d1 voltage changes from logic high to logic low or from logic low to logic high on d2 , the output stage switches on again, providing the temperature is below the overtemperature threshold limit minus the hysteresis. the fault status flag is reset (cleared) logic high.
motorola analog integrated circuit device data pc33886 13 package dimensions dh suffix (20-lead hsop) plastic package case 979c-02 issue a seating plane datum plane bottom view a x 45 e1 e d h e 18x b m bbb c 20 11 10 1 e2 notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per asme y14.5m, 1994. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. dimensions d and e1 do not include mold protrusion. allowable protrusion is 0.150 per side. dimensions d and e1 do include mold mismatch and are determined at datum plane -h-. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. 6. datums -a- and -b- to be determined at datum plane -h-. 7. dimension d does not include tiebar protrusions. allowable tiebar protrusions are 0.150 per side. d2 d1 e3 a2 section w-w b c1 b1 c e4 a m aaa c exposed heatsink area a b c h pin one id 10x y gauge plane detail y (1.600) l w w q bbb c l1 a1 a3 dim min max millimeters a 3.000 3.400 a1 0.100 0.300 a2 2.900 3.100 a3 0.00 0.100 d 15.800 16.000 d1 11.700 12.600 d2 0.900 1.100 e 13.950 14.450 e1 10.900 11.100 e2 2.500 2.700 e3 6.400 7.200 e4 2.700 2.900 l 0.840 1.100 l1 0.350 bsc b 0.400 0.520 b1 0.400 0.482 c 0.230 0.320 c1 0.230 0.280 e 1.270 bsc h --- 1.100 q 0 8 aaa 0.200 bbb 0.100 e/2
pc33886 motorola analog integrated circuit device data 14 notes
motorola analog integrated circuit device data pc33886 15 notes
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